10 nanometer

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In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.

All production "10 nm" processes are based on multi-gate FinFET technology, an evolution of silicon CMOS (MOSFET) technology. Samsung first started their production of 10 nm-class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10 nm chips in 2018.

Since 2009, however, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[1][2][3] For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[4] Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).[5][6] This means that transistor density (number of transistors per square millimeter) is more important than transistor size, since smaller transistors no longer necesarily mean improved performance, or an increase in the number of transistors.

Background[edit]

In 2002, a team of researchers consisting of TSMC researcher Chenming Hu and UC Berkeley researchers including B. Yu, Leland Chang, Shibly Ahmed, Cyrus Tabery, Tsu-Jae King Liu and Jeffrey Bokor described a 10 nm FinFET process.[7][8]

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.

In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the 10 nm node.[9][10]

In 2011, Samsung announced plans to introduce the 10 nm process the following year.[11] In 2012, Samsung announced eMMC flash memory chips that are produced using the 10 nm process.[12]

In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node,[13] mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.

There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.

Technology production history[edit]

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10 nm-class process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm".[14] On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm.[15] The technology's main announced challenge has been triple patterning for its metal layer.[16][17]

TSMC began commercial production of 10 nm chips in early 2016, before moving onto mass production in early 2017.[18]

On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor.[19] On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.[20]

On September 12, 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.

In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019.[21] In July the exact time was further pinned down to the holiday season.[22] In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.[23]

In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14nm and 10nm technology. 11LPP is based on their 10nm BEOL, not their 20nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.[24][25]

10 nm process nodes[edit]

Foundry[edit]

ITRS Logic Device
Ground Rules (2015)
Samsung TSMC Intel
(limited)
Process name 16/14 nm 11/10 nm 10 nm 11 nm 8nm 10 nm 10 nm[a]
Transistor density (MTr / mm²) Unknown Unknown 51.82[25] 54.38[25] 61.18[25] 52.51[27] 100.8[28][b]
Transistor Gate Pitch (nm) 70 48 68 ? 64 66 54
Interconnect pitch (nm) 56 36 51 ? ? 44 36
Transistor Fin Pitch (nm) 42 36 42 ? 42 36 34
Transistor Fin Height (nm) 42 42 49 ? ? Unknown 53
Production year 2015 2017 2013[14] 2018 2018 2016[18] 2018
  1. ^ Measurements of the process used for Cannon Lake in 2018. It is unclear whether these will be the same for Intel's next 10nm process in 2019.[26]
  2. ^ Intel uses this formula:[29]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.[30][31][32][33][34]

DRAM[edit]

For the DRAM industry, the "10 nm" node is often referred to as "10 nm-class" and this dimension generally refers to the half-pitch of the active area.[citation needed] The "10 nm" foundry structures are generally much larger.[citation needed] Samsung is also the most prominent player for 10 nm-class DRAM.[35][failed verification]

References[edit]

  1. ^ Shukla, Priyank. "A Brief History of Process Node Evolution". design-reuse.com. Retrieved 2019-07-09.
  2. ^ Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…". ExtremeTech.
  3. ^ "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". wccftech.com.
  4. ^ "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". eejournal.com.
  5. ^ https://en.wikichip.org/wiki/10_nm_lithography_process#Industry
  6. ^ https://en.wikichip.org/wiki/14_nm_lithography_process#Industry
  7. ^ Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Retrieved 9 July 2019.
  8. ^ Ahmed, S.; Bell, S.; Tabery, C.; Bokor, J.; Kyser, D.; Hu, C.; Bokor, J. (December 2002). "FinFET scaling to 10 nm gate length". Digest. International Electron Devices Meeting: 251–254. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2.
  9. ^ Damon Poeter (July 2008). "Intel's Gelsinger Sees Clear Path To 10nm Chips". Archived from the original on 2009-06-22. Retrieved 2009-06-20.
  10. ^ "MIT: Optical lithography good to 12 nanometers". Archived from the original on 2009-06-22. Retrieved 2009-06-20.
  11. ^ "World's Largest Fabrication Facility, Line-16". Samsung. September 26, 2011. Retrieved 21 June 2019.
  12. ^ "Samsung's new 10nm-process 64GB mobile flash memory chips are smaller, faster, better". Engadget. November 15, 2012. Retrieved 21 June 2019.
  13. ^ 10nm rollout
  14. ^ a b "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Retrieved 21 June 2019.
  15. ^ Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology, Oct 2016
  16. ^ Samsung 10nm announcement
  17. ^ triple patterning for 10nm metal
  18. ^ a b "10nm Technology". TSMC. Retrieved 30 June 2019.
  19. ^ "Buy".
  20. ^ techinsights.com. "10nm Rollout Marching Right Along". www.techinsights.com. Archived from the original on 2017-08-03. Retrieved 2017-06-30.
  21. ^ "Intel Corp. Delays 10nm Chip Production - Mass production is now scheduled for 2019". 2018-04-29. Retrieved 2018-08-01.
  22. ^ "Intel says not to expect mainstream 10nm chips until 2H19". 2018-07-28. Retrieved 2018-08-01.
  23. ^ "Intel's First 10nm Processor Lands In China". 2018-05-15. Retrieved 2018-09-11.
  24. ^ "VLSI 2018: Samsung's 11nm nodelet, 11LPP". WikiChip Fuse. 2018-06-30. Retrieved 2019-05-31.
  25. ^ a b c d "VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension". WikiChip Fuse. 2018-07-01. Retrieved 2019-05-31.
  26. ^ Demerjian, Charlie (2018-08-02). "Intel guts 10nm to get it out the door". SemiAccurate. Retrieved 29 September 2018.
  27. ^ Schor, David (2019-04-16). "TSMC Announces 6-Nanometer Process". WikiChip Fuse. Retrieved 2019-05-31.
  28. ^ "Intel 10nm density is 2.7X improved over its 14nm node". HEXUS. Retrieved 2018-11-14.
  29. ^ Bohr, Mark (2017-03-28). "Let's Clear Up the Node Naming Mess". Intel Newsroom. Retrieved 2018-12-06.
  30. ^ "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals". 2017-03-28.
  31. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Retrieved 2018-12-27.
  32. ^ "14nm 16nm 10nm and 7nm - What we know now".
  33. ^ "Qualcomm Snapdragon 835 First to 10 nm". Samsung 10LPE process
  34. ^ "10 nm lithography process". wikichip.
  35. ^ Samsung 10nm-class LPDDR4X


Preceded by
14 nm
MOSFET manufacturing processes (FinFET) Succeeded by
7 nm