90 nanometer

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search

The 90 nanometer (90 nm) process refers to the level of CMOS process technology that was reached by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, Fujitsu, TSMC, IBM, Elpida, Intel, AMD, Infineon, Texas Instruments and Micron Technology.

The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The 90 nm process was developed by Toshiba, Sony and Samsung during 2001–2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2 Gb NAND flash memory,[1][2] and then produced by Fujitsu in 2003[3] and TSMC in 2004.[4] The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90-nm node DRAM.[5]

Example: Elpida 90 nm DDR2 SDRAM process[edit]

Elpida Memory's 90 nm DDR2 SDRAM process.[6]

  • Use of 300 mm wafer size
  • Use of KrF (248 nm) lithography with optical proximity correction
  • 512 Mbit
  • 1.8 V operation
  • Derivative of earlier 110 nm and 100 nm processes

Processors using 90 nm process technology[edit]

See also[edit]

References[edit]

  1. ^ "Toshiba and Sony Make Major Advances in Semiconductor Process Technologies". Toshiba. 3 December 2002. Retrieved 26 June 2019.
  2. ^ "Our Proud Heritage from 2000 to 2009". Samsung Semiconductor. Samsung. Retrieved 25 June 2019.
  3. ^ 65nm CMOS Process Technology
  4. ^ "90nm Technology". TSMC. Retrieved 30 June 2019.
  5. ^ "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
  6. ^ Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report
  7. ^ "EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Retrieved 26 June 2019.

External links[edit]


Preceded by
130 nm
CMOS manufacturing processes Succeeded by
65 nm